Accueil > Electronique > FPGA > ContrÃ´leur I2C

ContrÃ´leur I2C

samedi 23 juin 2007, par Steve

Introduction

La description qui suit est un contrÃ´leur de bus I2C Ã©lÃ©mentaire. Il ne gÃ¨re pas le mode multi-maÃ®tre, toutefois le Â« clock strechingÂ » est pris en charge.
La frÃ©quence de transmission est dÃ©fini grÃ¢ce Ã un dÃ©compteur externe Ã la description.

DÃ©coupage

Le contrÃ´leur est dÃ©coupÃ© en plusieurs sÃ©quenceurs dont la liste exhaustive est la suivante :
le sÃ©quenceur de requÃªte,
le dÃ©tecteur d’Ã©vÃ©nements de bus,
le sÃ©quenceur de bus,
le contrÃ´leur de bus et
une bascule RSC.

Chaque unitÃ© sera dÃ©crite dans les dÃ©tails ci-dessous.

Le sÃ©quenceur de requÃªte

Cette description prend en charge le sÃ©quencement des actions sur le bus, Ã savoir :
la condition de â€œStartâ€ (start_req),
la condition de â€œRepeat Startâ€ (repeat_start_req),
la condition de â€œStopâ€ (stop_req) et
la gÃ©nÃ©ration de l’horloge lors de la transmission des donnÃ©es (byte_req).

Le bloc a besoin de connaÃ®tre :
l’Ã©tat du bus (busy) et
l’Ã©tat de l’action (complete).

Et il fournit :
la demande d’exÃ©cution de la condition de â€œStartâ€ (process_start),
la demande d’exÃ©cution de la condition de â€œRepeat Startâ€ (process_repeat_start),
la demande d’exÃ©cution de la condition de â€œStopâ€ (process_stop),
la demande d’exÃ©cution du signal d’horloge et
l’Ã©tat d’activitÃ© des actions de bus.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bus_state_seq is
  port ( \~CLR\               : in  std_logic;
         clk                  : in  std_logic;
         busy                 : in  std_logic;
         start_req            : in  std_logic;
         repeat_start_req     : in  std_logic;
         stop_req             : in  std_logic;
         byte_req             : in  std_logic;
         complete             : in  std_logic;
         in_progress          : out std_logic;
         process_start        : out std_logic;
         process_repeat_start : out std_logic;
         process_stop         : out std_logic;
         process_byte         : out std_logic);
end bus_state_seq;

architecture Behavioral of bus_state_seq is

  signal   state              : std_logic_vector(5 downto 0);
  constant idle_state         : std_logic_vector(state'range) := "000000";
  constant start_state        : std_logic_vector(state'range) := "010001";
  constant busy_state         : std_logic_vector(state'range) := "100000";
  constant repeat_start_state : std_logic_vector(state'range) := "010010";
  constant byte_state         : std_logic_vector(state'range) := "011000";
  constant stop_state         : std_logic_vector(state'range) := "010100";

  begin
    process (\~CLR\, clk)
    begin
      if (\~CLR\ = '0') then
        state <= idle_state;
      elsif (rising_edge(clk)) then
        case state is
          when idle_state =>
            if ((start_req = '1') and (busy = '0')) then
              state <= start_state;
            end if;
          when start_state =>
            if (complete = '1') then
              state <= busy_state;
            end if;
          when busy_state =>
            if (repeat_start_req = '1') then
              state <= repeat_start_state;
            end if;
            if (byte_req = '1') then
              state <= byte_state;
            end if;
            if (stop_req = '1') then
              state <= stop_state;
            end if;
          when repeat_start_state =>
            if (complete = '1') then
              state <= busy_state;
            end if;
          when byte_state =>
            if (complete = '1') then
              state <= busy_state;
            end if;
          when stop_state =>
            if (complete = '1') then
              state <= idle_state;
            end if;
          when others =>
            state <= idle_state;
        end case;
      end if;
    end process;
    process_start <= state(0);
    process_repeat_start <= state(1);
    process_stop <= state(2);
    process_byte <= state(3);
    in_progress <= state(4);
  end Behavioral;

Le dÃ©tecteur d’Ã©vÃ©nements de bus

Cette description permet de dÃ©tecter une condition de â€œStartâ€ ou â€œRepeat Startâ€ , une condition de â€œStopâ€ , le front montant du signal d’horloge ou le front descendant du signal d’horloge.
Ces informations sont importantes pour le sÃ©quencement de certains unitÃ©s.

library ieee;
use ieee.std_logic_1164.all;

entity event_detector is
  port ( \~CLR\      : in  std_logic;
         clk         : in  std_logic;
         sda         : in  std_logic;
         scl         : in  std_logic;
         start       : out std_logic;
         stop        : out std_logic;
         re          : out std_logic;
         fe          : out std_logic);
end event_detector;

architecture behavioral of event_detector is

  signal old_sda : std_logic;
  signal old_scl : std_logic;

  begin
    process (\~CLR\, clk)
    begin
      if (\~CLR\ = '0') then
        old_sda <= '1';
        old_scl <= '1';
      elsif (rising_edge(clk)) then
        old_sda <= sda;
        old_scl <= scl;
        start <= scl and old_sda and not(sda);
        stop <= scl and not(old_sda) and sda;
        re <= not(old_scl) and scl;
        fe <= old_scl and not(scl);
      end if;
    end process;
  end behavioral;

Le sÃ©quenceur de bus

Cette description permet de gÃ©nÃ©rer :
la condition de â€œStartâ€ ,
la condition de â€œRepeat Startâ€ ,
la condition de â€œStopâ€ ,
le signal d’horloge nÃ©cessaire aux Ã©changes de donnÃ©es.

Lors de la gÃ©nÃ©ration d’horloge, le bloc nÃ©cessite l’Ã©tat du signal â€œSCLâ€ afin de traiter le cas du â€œclock strechâ€ .
En effet, lorsque le sÃ©quenceur impose un niveau haut sur l’horloge, il attend que le signal passe effectivement Ã un avant de lancer un processus extÃ©rieur de temporisation.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bus_seq is
  port ( \~CLR\               : in  std_logic;
         clk                  : in  std_logic;
         process_start        : in  std_logic;
         process_repeat_start : in  std_logic;
         process_stop         : in  std_logic;
         process_byte         : in  std_logic;
         bo_cnt               : in  std_logic;
         scl                  : in  std_logic;
         s_sda                : out std_logic;
         r_sda                : out std_logic;
         s_scl                : out std_logic;
         r_scl                : out std_logic;
         clr_cnt              : out std_logic;
         complete             : out std_logic);
end bus_seq;

architecture Behavioral of bus_seq is

  signal   counter            : std_logic_vector(3 downto 0);
  signal   state              : std_logic_vector(7 downto 0);
  constant idle               : std_logic_vector(state'range) := "00000000";
  constant repeat_start_step0 : std_logic_vector(state'range) := "00010010";
  constant repeat_start_step1 : std_logic_vector(state'range) := "00000010";
  constant repeat_start_step2 : std_logic_vector(state'range) := "00011000";
  constant repeat_start_step3 : std_logic_vector(state'range) := "00001000";
  constant start_step0        : std_logic_vector(state'range) := "00011010";
  constant start_step1        : std_logic_vector(state'range) := "00001010";
  constant start_step2        : std_logic_vector(state'range) := "00010001";
  constant start_step3        : std_logic_vector(state'range) := "00000001";
  constant start_step4        : std_logic_vector(state'range) := "00010100";
  constant start_step5        : std_logic_vector(state'range) := "00000100";
  constant start_step6        : std_logic_vector(state'range) := "00100000";
  constant stop_step0         : std_logic_vector(state'range) := "00010101";
  constant stop_step1         : std_logic_vector(state'range) := "00000101";
  constant stop_step2         : std_logic_vector(state'range) := "01011000";
  constant stop_step3         : std_logic_vector(state'range) := "01001000";
  constant stop_step4         : std_logic_vector(state'range) := "01010010";
  constant stop_step5         : std_logic_vector(state'range) := "01000010";
  constant stop_step6         : std_logic_vector(state'range) := "01100000";
  constant byte_step0         : std_logic_vector(state'range) := "10010100";
  constant byte_step1         : std_logic_vector(state'range) := "10000100";
  constant byte_step2         : std_logic_vector(state'range) := "10011000";
  constant byte_step3         : std_logic_vector(state'range) := "10001000";
  constant byte_step4         : std_logic_vector(state'range) := "11010100";
  constant byte_step5         : std_logic_vector(state'range) := "00100100";

  begin
    process (\~CLR\, clk)
    begin
      if (\~CLR\ = '0') then
        state <= idle;
        counter <= (others => '0');
      elsif (rising_edge(clk)) then
        case state is
          when idle =>
            if (process_start = '1') then
              state <= start_step0;
            end if;
            if (process_repeat_start = '1') then
              state <= repeat_start_step0;
            end if;
            if (process_stop = '1') then
              state <= stop_step0;
            end if;
            if (process_byte = '1') then
              state <= byte_step0;
            end if;
          when repeat_start_step0 =>
            state <= repeat_start_step1;
          when repeat_start_step1 =>
            if (bo_cnt = '1') then
              state <= repeat_start_step2;
            end if;
          when repeat_start_step2 =>
            state <= repeat_start_step3;
          when repeat_start_step3 =>
            if (bo_cnt = '1') then
              state <= start_step2;
            end if;
          when start_step0 =>
            state <= start_step1;
          when start_step1 =>
            if (bo_cnt = '1') then
              state <= start_step2;
            end if;
          when start_step2 =>
            state <= start_step3;
          when start_step3 =>
            if (bo_cnt = '1') then
              state <= start_step4;
            end if;
          when start_step4 =>
            state <= start_step5;
          when start_step5 =>
            if (bo_cnt = '1') then
              state <= start_step6;
            end if;
          when start_step6 =>
            state <= idle;
          when stop_step0 =>
            state <= stop_step1;
          when stop_step1 =>
            if (bo_cnt = '1') then
              state <= stop_step2;
            end if;
          when stop_step2 =>
            state <= stop_step3;
          when stop_step3 =>
            if (bo_cnt = '1') then
              state <= stop_step4;
            end if;
          when stop_step4 =>
            state <= stop_step5;
          when stop_step5 =>
            if (bo_cnt = '1') then
              state <= stop_step6;
            end if;
          when stop_step6 =>
            state <= idle;
          when byte_step0 => 
            counter <= (others => '0');
            state <= byte_step1;
          when byte_step1 =>
            if (bo_cnt = '1') then
              state <= byte_step2;
            end if;
          when byte_step2 =>
            if (scl /= '0') then
              state <= byte_step3;
            end if;
          when byte_step3 =>
            if (bo_cnt = '1') then
              state <= byte_step4;
            end if;
          when byte_step4 =>
            counter <= counter + 1;
            if (counter = 8) then
              state <= byte_step5;
            else
              state <= byte_step1;
            end if;
          when byte_step5 =>
            state <= idle;
          when others =>
            state <= idle;
        end case;
      end if;
    end process;
    r_sda <= state(0);
    s_sda <= state(1);
    r_scl <= state(2);
    s_scl <= state(3);
    clr_cnt <= state(4);
    complete <= state(5);
  end behavioral;

Le contrÃ´leur de bus

Cette description permet de :
dÃ©tecter la direction du transfert,
indiquer l’instant oÃ¹ doit se produire l’acquittement et
fournir l’Ã©tat du bus.

Le bloc utilise les signaux â€œstartâ€ et â€œstopâ€ pour indiquer l’Ã©tat du bus. Le signal interne â€œfirstâ€ associÃ© au compteur interne et au signal â€œsdaâ€ permet de dÃ©tecter la direction du transfert. Le compteur est aussi utilisÃ© pour dÃ©tecter l’instant oÃ¹ les acquittements doivent se produire.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bus_ctrl is
  port ( \~CLR\           : in  std_logic;
         clk              : in  std_logic;
         sda              : in  std_logic;
         start            : in  std_logic;
         stop             : in  std_logic;
         re               : in  std_logic;
         fe               : in  std_logic;
         acktime          : out std_logic;
         write            : out std_logic;
         busy             : out std_logic);
end bus_ctrl;

architecture Behavioral of bus_ctrl is

  signal internal   : std_logic;
  signal must_count : std_logic;
  signal direction  : std_logic;
  signal first      : std_logic;
  signal counter    : std_logic_vector(3 downto 0);

  begin
    process (\~CLR\, clk)
    begin
      if (\~CLR\ = '0') then
        internal <= '0';
        counter <= (others => '0');
        must_count <= '0';
        acktime <= '0';
        direction <= '0';
        write <= '0';
        first <= '1';
      elsif (rising_edge(clk)) then
        if (start = '1') then
          internal <= '1';
          counter <= (others => '0');
          must_count <= '0';
          direction <= '0';
          write <= '0';
          first <= '1';
        end if;
        if (stop = '1') then
          internal <= '0';
        end if;
        if (fe = '1') then
          if (must_count = '1') then
            if (counter = 8) then
              counter <= (others => '0');
              acktime <= '0';
              if (first = '1') then
                write <= direction;
                first <= '0';
              end if;
            elsif (counter = 7) then
              counter <= counter + 1;
              acktime <= '1';
            else
              counter <= counter + 1;
            end if;
          else
            must_count <= '1';
          end if;
        end if;
        if (re = '1') then
          if (counter = 7) then
            direction <= sda;
          end if;
        end if;
      end if;
    end process;
    busy <= internal;
  end Behavioral;

La bascule RS

Voici la description VHDL de la bascule :

library ieee;
use ieee.std_logic_1164.all;

entity rsc is
  port ( \~CLR\ : in  std_logic;
         clk    : in  std_logic;
         s      : in  std_logic;
         r      : in  std_logic;
         q      : out std_logic);
end rsc;

architecture behavioral of rsc is

  begin
    process (\~CLR\, clk)
    begin
      if (\~CLR\ = '0') then
        q <= '1';
      elsif (rising_edge(clk)) then
        if (s = '1') then
          q <= '1';
        elsif (r = '1') then
          q <= '0';
        end if;
      end if;
    end process;
  end behavioral;

Le contrÃ´leur de bus I2C

Le contrÃ´leur de bus I2C est composÃ© de toutes les descriptions ci-dessus auxquels on ajoute un multiplexeur pour la gÃ©nÃ©ration du signal SDA en sortie, un premier registre Ã dÃ©calage pour l’Ã©mission et un second pour la rÃ©ception ainsi que deux blocs de synchronisation pour les signaux SDA et SCL en entrÃ©e.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity master_i2c is
  port ( \~CLR\           : in  std_logic;
         clk              : in  std_logic;
         start_req        : in  std_logic;
         repeat_start_req : in  std_logic;
         stop_req         : in  std_logic;
         byte_req         : in  std_logic;
         d                : in  std_logic_vector(7 downto 0);
         ackin            : in  std_logic;
         sda_in           : in  std_logic;
         scl_in           : in  std_logic;
         bo_cnt           : in  std_logic;
         clr_cnt          : out std_logic;
         sda_out          : out std_logic;
         scl_out          : out std_logic;
         busy             : out std_logic;
         in_progress      : out std_logic;
         q                : out std_logic_vector(7 downto 0);
         ackout           : out std_logic);
end master_i2c;

architecture Behavioral of master_i2c is


  component bus_state_seq
    port ( \~CLR\               : in  std_logic;
           clk                  : in  std_logic;
           busy                 : in  std_logic;
           start_req            : in  std_logic;
           repeat_start_req     : in  std_logic;
           stop_req             : in  std_logic;
           byte_req             : in  std_logic;
           complete             : in  std_logic;
           in_progress          : out std_logic;
           process_start        : out std_logic;
           process_repeat_start : out std_logic;
           process_stop         : out std_logic;
           process_byte         : out std_logic);
  end component;

  component event_detector
    port ( \~CLR\      : in  std_logic;
           clk         : in  std_logic;
           sda         : in  std_logic;
           scl         : in  std_logic;
           start       : out std_logic;
           stop        : out std_logic;
           re          : out std_logic;
           fe          : out std_logic);
  end component;

  component bus_seq
    port ( \~CLR\               : in  std_logic;
           clk                  : in  std_logic;
           process_start        : in  std_logic;
           process_repeat_start : in  std_logic;
           process_stop         : in  std_logic;
           process_byte         : in  std_logic;
           bo_cnt               : in  std_logic;
           scl                  : in  std_logic;
           s_sda                : out std_logic;
           r_sda                : out std_logic;
           s_scl                : out std_logic;
           r_scl                : out std_logic;
           clr_cnt              : out std_logic;
           complete             : out std_logic);
  end component;

  component bus_ctrl
    port ( \~CLR\           : in  std_logic;
           clk              : in  std_logic;
           sda              : in  std_logic;
           start            : in  std_logic;
           stop             : in  std_logic;
           re               : in  std_logic;
           fe               : in  std_logic;
           acktime          : out std_logic;
           write            : out std_logic;
           busy             : out std_logic);
  end component;

  component rsc
    port ( \~CLR\ : in  std_logic;
           clk    : in  std_logic;
           s      : in  std_logic;
           r      : in  std_logic;
           q      : out std_logic);
  end component;

  signal internal_busy        : std_logic;
  signal complete             : std_logic;
  signal process_start        : std_logic;
  signal process_repeat_start : std_logic;
  signal process_stop         : std_logic;
  signal process_byte         : std_logic;
  signal start                : std_logic;
  signal stop                 : std_logic;
  signal re                   : std_logic;
  signal fe                   : std_logic;
  signal s_sda                : std_logic;
  signal r_sda                : std_logic;
  signal s_scl                : std_logic;
  signal r_scl                : std_logic;
  signal acktime              : std_logic;
  signal write                : std_logic;
  signal sda_bs               : std_logic;
  signal outgoing             : std_logic_vector(8 downto 0);
  signal incoming             : std_logic_vector(8 downto 0);
  signal sda                  : std_logic_vector(1 downto 0);
  signal scl                  : std_logic_vector(1 downto 0);

  begin
    inst_bss     : bus_state_seq  port map (\~CLR\, clk, internal_busy, start_req, repeat_start_req, stop_req, byte_req, complete, in_progress, process_start, process_repeat_start, process_stop, process_byte);
    inst_ed      : event_detector port map (\~CLR\, clk, sda(1), scl(1), start, stop, re, fe);
    inst_bs      : bus_seq        port map ( \~CLR\, clk, process_start, process_repeat_start, process_stop, process_byte, bo_cnt, scl(1), s_sda, r_sda, s_scl, r_scl, clr_cnt, complete);
    inst_bc      : bus_ctrl       port map ( \~CLR\, clk, sda(1), start, stop, re, fe, acktime, write, internal_busy);
    inst_rsc_sda : rsc            port map ( \~CLR\, clk, s_sda, r_sda, sda_bs);
    inst_rsc_scl : rsc            port map ( \~CLR\, clk, s_scl, r_scl, scl_out);

    sda_out <= sda_bs when (process_byte = '0') else
               '1' when ((write /= '0') xor (acktime = '1')) else
               outgoing(8);

    process (\~CLR\, clk)
      begin
        if (\~CLR\ = '0') then
          outgoing <= (others => '0');
          incoming <= (others => '0');
        elsif (rising_edge(clk)) then
          if (fe = '1') then
            outgoing <= outgoing(7 downto 0) & sda(1);
          elsif (byte_req = '1') then
            outgoing <= d & ackin;
          end if;
          if (re = '1') then
            incoming <= incoming(7 downto 0) & sda(1);
          end if;
        end if;
      end process;

    process (\~CLR\, clk)
      begin
        if (\~CLR\ = '0') then
          sda <= (others => '1');
          scl <= (others => '1');
        elsif (rising_edge(clk)) then
          sda <= sda(0) & sda_in;
          scl <= scl(0) & scl_in;
        end if;
      end process;

    busy <= internal_busy;
    q <= incoming(8 downto 1);
    ackout  <= incoming(0);
  end Behavioral;

ContrÃ´leur I2C

Introduction

DÃ©coupage

Le sÃ©quenceur de requÃªte

Le dÃ©tecteur d’Ã©vÃ©nements de bus

Le sÃ©quenceur de bus

Le contrÃ´leur de bus

La bascule RS

Le contrÃ´leur de bus I2C

Documents joints

Un message, un commentaire ?

Electronique

Dans la même rubrique